Analog MAP decoder for (8, 4) Hamming code in subthreshold CMOS

C. Winstead, Jie Dai, Woo Jin Kim, S. Little
June 2001

Abstract

An all-MOS analog implementation of a MAP decoder is presented for the (8, 4) extended Hamming code. This paper describes the design and analysis of a tail-biting trellis decoder implementation using subthreshold CMOS devices. A VLSI test chip has recently returned from fabrication, and preliminary test results indicate accurate decoding up to 20 MBit/s.

Type
Conference paper
Publication
International Symposium on Information Theory
decoding (8 4) Hamming code turbo codes VLSI circuit testing Hamming code analogue processing circuits all-MOS analog implementation analog MAP decoder Fabrication subthreshold CMOS subthreshold CMOS devices tail-biting trellis decoder VLSI test chip bipolar transistor circuit CMOS analog computers threshold voltage very large scale integration maximum a posteriori estimation
Jie Dai
Jie Dai

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